An 0.1-μm voidless double-deck-shaped (DDS) gate HJFET with reduced gate-fringing-capacitance

This paper describes a novel double-deck-shaped (DDS) gate technology for 0.1-mu m heterojunction FET's (HJFET's) which have about half the external gate fringing capacitance (C-f('ext)) Of conventional T-shaped gate HJFET's, By introducing a T-shaped SiO2-opening technique based on two-step dry-etching with W-film masks, we fabricated 0.1-mu m gate-openings which were suitable for reducing the C-f('ext) and filling gate-metals with voidless. The fine gate-openings are completely filled with refractory WSi/Ti/Pt/Au gate-metal by using WSi-collimated sputtering and electroless Au-plating, resulting in high performance 0.1-mu m DDS gate HJFET's we fabricated. The 0.1-mu m n-Al-0.2 Ga-0.8 As/i-In-0.15 Ga0.85As pseudomorphic DDS gate HJFET's exhibited an excellent V-th standard-deviation (sigma V-th) Of 39 mV because dry-etching techniques were used in all etching-processes. Also, an HJFET covered with SiO2 passivation film had very high performance with an fi of 120 GHz and an f(max) of 165 GHz, due to the low C-f('ext) with the DDS gate structure. In addition, a high fT of 151 GHz and an f(max) of 186 GHz were obtained without a SiO2 passivation him, This fabrication technology shows great promise for high-speed IC applications.