High quality voids free oxide deposition

As silicon devices shrink and their density increases, the use of a multilevel metal interconnect is inevitable. It becomes one of the major challenges in IC processing, to apply a quality interlevel dielectric layer over patterned Al lines with a high aspect ratio (>1.5). It requires a low temperature (<400 degrees C) deposition process while maintaining good material quality and electrical characteristics. In this paper, oxide deposition using silane (SiH4), tetraethylorthosilicate (TEOS), and tetramethylcyclotetra-siloxane (TMCTS) in various plasma reactors will be presented. We have compared the chemical radical and ion effects on the step coverage for high aspect ratio trench-filling applications. Profiles and the quality of oxide thin films deposited under various ion and radical effects will be presented. Biased ECR oxide deposition, which has flexibility in controlling ion density and ion energy, has demonstrated the capability of producing high quality oxide with no voids in filling high aspect ratio trenches. Reaction chemistries and the ion bombardment effects on the oxide profile will be discussed. Most importantly, the concerns of manufacturability of this promising technique will also be examined. These include particulate issues, deposition temperature control, and long-term device reliability issues.