Analytic Modeling of the Bias Temperature Instability Using Capture/Emission Time Maps

被引：151

作者：

Grasser, T. ^{[1
]}

Wagner, P. -J. ^{[1
]}

Reisinger, H. ^{[2
]}

Aichinger, Th ^{[3
]}

Pobegen, G. ^{[4
]}

Nelhiebel, M. ^{[5
]}

Kaczer, B.

机构：

[1] TU Wien, Inst Microelect, Vienna, Austria

[2] Infineon, Munich, Germany

[3] Penn State Univ, State Coll, PA 16801 USA

[4] KAI, Villach, Austria

[5] Infineon, Villach, Austria

来源：

2011 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2011年

基金：

奥地利科学基金会;

关键词：

NBTI; MECHANISMS;

D O I：

10.1109/IEDM.2011.6131624

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Despite a number of recent advances made in the understanding of the bias temperature instability (BTI), there is still no simple model available which can capture BTI degradation during DC or duty-factor (DF) dependent stress and the following recovery. By exploiting the intuitive features of the recently proposed capture/emission time (CET) maps [1, 2], we suggest an analytic model capable of handling a wide number of BTI stress and recovery patterns. As the model captures both the temperature- and bias- dependence of the degradation, it allows for realistic lifetime extrapolation. Compared to available models which do not consider the saturation of the degradation, our model predicts considerably more optimistic lifetimes.

引用

页数：4

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