A multigigabit DRAM technology with 6F2 open-bitline cell, distributed overdriven sensing, and stacked-flash fuse

被引：16

作者：

Takahashi, T ^{[1
]}

Sekiguchi, T

Takemura, R

Narui, S

Fujisawa, H

Miyatake, S

Morino, M

Arai, K

Yamada, S

Shukuri, S

Nakamura, M

Tadaki, Y

Kajigaya, K

Kimura, K

Itoh, K

机构：

[1] Elpida Memory Inc, Kanagawa 2291197, Japan

[2] Hitachi Ltd, Tokyo, Japan

[3] Hitachi ULSI Syst Co Ltd, Tokyo, Japan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2001年 / 36卷 / 11期

关键词：

array noise; DRAM; low voltage and high speed; memory cell; post-packaging repair;

D O I：

10.1109/4.962294

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A multigigabit DRAM technology was developed that features a low-noise 6F(2) open-bitline cell with fully utilized edge arrays, distributed overdriven sensing for operation below 1 V, and a highly reliable post-packaging repair scheme using a stacked-Flash fuse. This technology, which can be used to fabricate a 0.13-mum 180-mm(2) 1-Gb DRAM assembled in a 400-mil package, was verified using a 57.6-mm(2), 200-MHz array-cycle, 256-Mb test chip with 0.109-mum(2) cells.

引用

页码：1721 / 1727

页数：7

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