MOS transistors with stacked SiO2-Ta2O5-SiO2 gate dielectrics for giga-scale integration of CMOS technologies

Advances in lithography and thinner SiO2 gate oxides have enabled the scaling of MOS technologies to sub-0.25-mu m feature size. High dielectric constant materials, such as Ta2O5, have been suggested as a substitute for SiO2 as the gate material beyond t(ox) approximate to 25 Angstrom. However, the Si-Ta2O5 material system suffers from unacceptable levels of bulk fixed charge, high density of interface trap states, and low silicon interface carrier mobility. In this paper we present a solution to these issues through a novel synthesis of a thermally grown SiO2 (10 Angstrom)-Ta2O5 (MOCVD-50 Angstrom)- SiO2 (LPCVD-5 Angstrom) stacked dielectric, Transistors fabricated using this stacked gate dielectric exhibit excellent subthreshold behavior, saturation characteristics, and drive currents.