A comparison of quantum-mechanical capacitance-voltage simulators

被引：66

作者：

Richter, CA ^{[1
]}

Hefner, AR ^{[1
]}

Vogel, EM ^{[1
]}

机构：

[1] Natl Inst Stand & Technol, Div Semicond Elect, Gaithersburg, MD 20899 USA

来源：

IEEE ELECTRON DEVICE LETTERS | 2001年 / 22卷 / 01期

关键词：

capacitance; effective oxide thickness; gate dielectric; inversion quantization; MOS devices; polysilicon depletion;

D O I：

10.1109/55.892436

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have systematically compared the results of an extensive ensemble of the most advanced available quantum-mechanical capacitance-voltage (C-V) simulation and analysis packages for a range of metal-oxide-semiconductor device parameters. While all have similar trends accounting for polysilicon depletion and quantum-mechanical confinement, quantitatively, there is a difference of up to 20 % in the calculated accumulation capacitance for devices with ultrathin gate dielectrics. This discrepancy leads to large inaccuracies in the values of dielectric thickness extracted from capacitance measurements and illustrates the importance of consistency during C-V analysis and the need to fully report how such analysis is done.

引用

页码：35 / 37

页数：3

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