Dielectric pockets - A new concept of the junctions for deca-nanometric CMOS devices

被引：68

作者：

Jurczak, M

Skotnicki, T

Gwoziecki, R

Paoli, M

Tormen, B

Ribot, P

Dutartre, D

Monfray, S

Galvier, J

机构：

[1] France Telecom R&D, Grenoble, France

[2] ST Microelect, Agrate Brianza, Italy

[3] ST Microelect, F-38926 Crolles, France

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2001年 / 48卷 / 08期

关键词：

bulk punchthrough; CMOS architecture; halos; MOSFET; pockets; short-channel effects; silicon devices; threshold voltage;

D O I：

10.1109/16.936706

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new concept of dielectric pockets is proposed allowing suppression of short-channel effects (SCEs) and DIBL without increasing the channel doping. The dielectric pockets have been implanted into 0.15-mum PMOS devices showing substantial efficiency in reducing SCE and I-OFF current without altering the current drive. The dielectric pockets thus embody the ideal pocket architecture.

引用

页码：1770 / 1775

页数：6

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