Modelling background charge rearrangements near single-electron transistors as a Poisson process

Background charge rearrangements in metallic single-electron transistors are modelled in two-level tunnelling systems as a Poisson process with a scale parameter as only variable. The model explains the recent observation of asymmetric Coulomb bloc ade peak spacing distributions in metallic single-electron transistors. These distributions are consistent with charge trapping processes within impurities located between transistor island and gate. From the scale parameter determined, we estimate the average size of the tunnelling systems, their density of states, and the height of their energy barrier.