共 11 条
[1]
Lee Y, 2005, J IND ENG CHEM, V11, P27
[3]
A 45nm logic technology with high-k plus metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging
[J].
2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2,
2007,
:247-+
[4]
NARASIMHA S, 2006, IEDM, P689
[5]
NAYFEH HM, 2007, P DEV RES C, P51
[7]
Rim K, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P43, DOI 10.1109/IEDM.2002.1175775
[8]
Ritenour A, 2003, 2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, P433
[9]
Shang HL, 2004, IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, P157
[10]
Yamamoto T, 2007, INT EL DEVICES MEET, P1041