A 45nm logic technology with high-k plus metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging

被引：745

作者：

Mistry, K. ^{[1
]}

Allen, C. ^{[1
]}

Auth, C. ^{[1
]}

Beattie, B. ^{[1
]}

Bergstrom, D. ^{[1
]}

Bost, M. ^{[1
]}

Brazier, M. ^{[1
]}

Buehler, M. ^{[1
]}

Cappellani, A. ^{[1
]}

Chau, R. ^{[2
]}

Choi, C. -H. ^{[1
]}

Ding, G. ^{[1
]}

Fischer, K. ^{[1
]}

Ghani, T. ^{[1
]}

Grover, R. ^{[1
]}

Han, W. ^{[1
]}

Hanken, D. ^{[1
]}

Hatttendorf, M. ^{[1
]}

He, J. ^{[3
]}

Hicks, J. ^{[3
]}

Huessner, R. ^{[1
]}

Ingerly, D. ^{[1
]}

Jain, P. ^{[1
]}

James, R. ^{[1
]}

Jong, L. ^{[1
]}

Joshi, S. ^{[1
]}

Kenyon, C. ^{[1
]}

Kuhn, K. ^{[1
]}

Lee, K. ^{[1
]}

Liu, H. ^{[1
]}

Maiz, J. ^{[3
]}

McIntyre, B. ^{[1
]}

Moon, P. ^{[1
]}

Neirynck, J. ^{[1
]}

Pei, S. ^{[3
]}

Parker, C. ^{[1
]}

Parsons, D. ^{[1
]}

Prasad, C. ^{[3
]}

Pipes, L. ^{[1
]}

Prince, M. ^{[1
]}

Ranade, P. ^{[1
]}

Reynolds, T. ^{[1
]}

Sandford, J. ^{[1
]}

Schifren, L. ^{[4
]}

Sebastian, J. ^{[1
]}

Seiple, J. ^{[1
]}

Simon, D. ^{[1
]}

Sivakumar, S. ^{[1
]}

Smith, P. ^{[1
]}

Thomas, C. ^{[1
]}

机构：

[1] Intel Corp, Log Technol Dev, Hillsboro, OR 97124 USA

[2] Intel Corp, Comp Res, Hillsboro, OR 97124 USA

[3] Intel Corp, QRE, Hillsboro, OR 97124 USA

[4] Intel Corp, TCAD, Hillsboro, OR 97124 USA

来源：

2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2 | 2007年

关键词：

D O I：

10.1109/IEDM.2007.4418914

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

A 45nm logic technology is described that for the first time incorporates high-k+metal gate transistors in a high volume manufacturing process. The transistors feature 1.0nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153Mb SRAM arrays with SRAM cell size of 0.346 mu m(2), and on multiple microprocessors.

引用

页码：247 / +

页数：2

共 9 条

[1] A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm2 SRAM cell [J].

Bai, P ;

Auth, C ;

Balakrishnan, S ;

Bost, M ;

Brain, R ;

Chikarmane, V ;

Heussner, R ;

Hussein, M ;

Hwang, J ;

Ingerly, D ;

James, R ;

Jeong, J ;

Kenyon, C ;

Lee, E ;

Lee, SH ;

Lindert, N ;

Liu, M ;

Ma, Z ;

Marieb, T ;

Murthy, A ;

Nagisetty, R ;

Natarajan, S ;

Neirynck, J ;

Ott, A ;

Parker, C ;

Sebastian, J ;

Shaheed, R ;

Sivakurnar, S ;

Steigerwald, J ;

Tyagi, S ;

Weber, C ;

Woolery, B ;

Yeoh, A ;

Zhang, K ;

Bohr, M .

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, :657-660

[2] High-κ/metal-gate stack and its MOSFET characteristics [J].

Chau, R ;

Datta, S ;

Doczy, M ;

Doyle, B ;

Kavalieros, J ;

Metz, M .

IEEE ELECTRON DEVICE LETTERS, 2004, 25 (06) :408-410

[3]

Hobbs C., 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407), P9, DOI 10.1109/VLSIT.2003.1221060

[4] Inversion mobility and gate leakage in high-k/metal gate MOSFETs [J].

Kotlyar, R ;

Giles, MD ;

Matagne, P ;

Obradovic, B ;

Shrifen, L ;

Stettler, M ;

Wang, E .

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, :391-394

[5] Issues in high-κ gate stack interfaces [J].

Misra, V ;

Lucovsky, G ;

Parsons, GN .

MRS BULLETIN, 2002, 27 (03) :212-216

[6]

Mistry K, 2004, 2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P50

[7] Review on high-k dielectrics reliability issues [J].

Ribes, G ;

Mitard, J ;

Denais, M ;

Bruyere, S ;

Monsieur, F ;

Parthasarathy, C ;

Vincent, E ;

Ghibaudo, G .

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2005, 5 (01) :5-19

[8] Impact of oxygen vacancies on high-κ gate stack engineering [J].

Takeuchi, H ;

Wong, HY ;

Ha, DW ;

King, TJ .

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, :829-832

[9]

Tyagi S, 2005, INT EL DEVICES MEET, P1070

← 1 →