Nanoscale CMOS

被引:309
作者
Wong, HSP [1 ]
Frank, DJ [1 ]
Solomon, PM [1 ]
Wann, CHJ [1 ]
Welser, JJ [1 ]
机构
[1] IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA
关键词
CMOS; device technology; memory; MOS; MOSFET; nanotechnology; scaling; ultralarge scale integration (ULSI); very large scale integration (VLSI);
D O I
10.1109/5.752515
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper examines the apparent limits, possible extensions, and applications of CMOS technology in the nanometer regime. Starting from device scaling theory and current industry projections, we analyze the achievable performance and possible limits of CMOS technology from the point of view of device physics, device technology, and power consumption. Various possible extentions to the basic logic and memory devices are reviewed, with emphasis on novel devices that are structurally distinct from conventional bulk CMOS logic and memory devices. Possible applications of nanoscale CMOS are examined, with a view to better defining the likely capabilities of future microelectronic systems. This analysis covers both data processing applications and nondata processing applications such as RF and imaging. Finally, we speculate on the future of CMOS for the coming 15-20 years.
引用
收藏
页码:537 / 570
页数:36
相关论文
共 181 条
[1]   Camera on a chip [J].
Ackland, B ;
Dickinson, A .
1996 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS, 1996, 39 :22-25
[2]  
ACKLAND B, 1993, P CUST INT CIRC C
[3]   THE EVOLUTION OF IBM CMOS DRAM TECHNOLOGY [J].
ADLER, E ;
DEBROSSE, JK ;
GEISSLER, SF ;
HOLMES, SJ ;
JAFFE, MD ;
JOHNSON, JB ;
KOBURGER, CW ;
LASKY, JB ;
LLOYD, B ;
MILES, GL ;
NAKOS, JS ;
NOBLE, WP ;
VOLDMAN, SH ;
ARMACOST, M ;
FERGUSON, R .
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1995, 39 (1-2) :167-188
[4]   ELECTRONIC-PROPERTIES OF TWO-DIMENSIONAL SYSTEMS [J].
ANDO, T ;
FOWLER, AB ;
STERN, F .
REVIEWS OF MODERN PHYSICS, 1982, 54 (02) :437-672
[5]   Technology challenges for integration near and below 0.1 mu m [J].
Asai, S ;
Wada, Y .
PROCEEDINGS OF THE IEEE, 1997, 85 (04) :505-520
[6]   A DYNAMIC THRESHOLD VOLTAGE MOSFET (DTMOS) FOR VERY-LOW VOLTAGE OPERATION [J].
ASSADERAGHI, F ;
PARKE, S ;
SINITSKY, D ;
BOKOR, J ;
KO, PK ;
HU, CM .
IEEE ELECTRON DEVICE LETTERS, 1994, 15 (12) :510-512
[7]   A 7.9/5.5psec room/low temperature SOI CMOS [J].
Assaderaghi, F ;
Rausch, W ;
Ajmera, A ;
Leobandung, E ;
Schepis, D ;
Wagner, L ;
Wann, HJ ;
Bolam, J ;
Yee, D ;
Davari, B ;
Shahidi, G .
INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, :415-418
[8]   SOI: Materials to systems [J].
AubertonHerve, AJ .
IEDM - INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST 1996, 1996, :3-10
[9]   Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's [J].
Auth, CP ;
Plummer, JD .
IEEE ELECTRON DEVICE LETTERS, 1997, 18 (02) :74-76
[10]  
BHAVNAGARWALA AJ, 1996 ISLPED, P193