A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation

被引：354

作者：

Leung, KN ^{[1
]}

Mok, PKT ^{[1
]}

机构：

[1] Hong Kong Univ Sci & Technol, Dept Elect & Elect Engn, Hong Kong, Peoples R China

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2003年 / 38卷 / 10期

关键词：

damping-factor-control frequency compensation; loop-gain stability; capacitor-free low-dropout regulator (LDO); CMOS voltage reference;

D O I：

10.1109/JSSC.2003.817256

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 1.5-V 100-mA capacitor-free CMOS low-dropout regulator (LDO) for system-on-chip applications to reduce board space and external pins is presented. By utilizing damping-factor-control frequency compensation on the advanced LDO structure, the proposed LDO provides high stability, as well as fast line and load transient responses, even in capacitor-free operation. The proposed LDO has been implemented in a commercial 0.6-mum CMOS technology, and the active chip area is 568 mum x 541 mum. The total error of the output voltage due to line and load variations is less than +/-0.25%, and the temperature coefficient is 38 ppm/degreesC. Moreover, the output voltage can recover within 2 mus for full load-current changes. The power-supply rejection ratio at 1 MHz is -30 dB, and the output noise spectral densities at 100 Hz and 100 kHz are 1.8 and 0.38 muV/rootHz, respectively.

引用

页码：1691 / 1702

页数：12

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