Monte Carlo simulation of hot-carrier degradation in scaled MOS transistors for VLSI technology

被引：5

作者：

Ghetti, A ^{[1
]}

Bude, J ^{[1
]}

Liu, CT ^{[1
]}

机构：

[1] AT&T Bell Labs, Lucent Technol, Murray Hill, NJ 07974 USA

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST | 1998年

关键词：

D O I：

10.1109/IEDM.1998.746498

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper investigates the hot electron (HE) reliability of ultra thin gate oxide nMOSFETs by means of Full Band Monte Carlo (FBMC) simulation. First, a qualitative explanation of the smaller hot electron induced degradation (HEID) for thinner oxides observed in [1] is presented. Then, HEID in two different types of nMOSFET suitable for sub-0.1 mu m applications is analyzed as the devices are properly scaled below O.1 mu m, addressing the question whether gate oxide thickness can be scaled down to 1nm from the hot electron degradation point of view. Finally, the validity of usual extrapolation techniques of HEID lifetime from experimental data usually available in the range 2.5V less than or equal to V-DD less than or equal to 5V to low voltages is addressed.

引用

页码：893 / 896

页数：4

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