Effects of Si-cap layer thinning and Ge segregation on the characteristics of Si/SiGe/Si heterostructure pMOSFETs

被引：22

作者：

Song, YJ ^{[1
]}

Lim, JW ^{[1
]}

Kim, SH ^{[1
]}

Bae, HC ^{[1
]}

Kang, JY ^{[1
]}

Park, KW ^{[1
]}

Shim, KH ^{[1
]}

机构：

[1] Elect & Telecommun Res Inst, Wireless Commun Device Res Grp, SiGe Device Team, Yuseong Gu, Taejon 305350, South Korea

来源：

SOLID-STATE ELECTRONICS | 2002年 / 46卷 / 11期

关键词：

Si/SiGe/Si heterostructure; MOSFET; Si-cap layer; Ge segregation; interface state density; transconductance;

D O I：

10.1016/S0038-1101(02)00139-9

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have investigated the influence of Si-cap thickness and Ge segregation on the device properties of Si/SiGe/Si heterostructure pMOSFETs to optimize the device design. It is found that the thermal gate-oxide quality is degraded abruptly during the Si-cap thinning because Ge segregation proceeds rapidly beyond a certain critical thickness. However, it is noted that the significant increase in interface state density (D-it) occurs only if the Ge concentration at the oxide interface is high enough (similar to1.8 x 10(22) cm(-3)). If D-it is kept low (<5.0 x 10(10) cm(-2) eV(-1)), a thinner Si cap improves device's transconductance, on-state current, threshold voltage, and subthreshold swing owing to the larger oxide-to-channel capacitance, less parallel channel effect, and higher degree of valence band bending. Finally, the Si-cap thickness should be controlled precisely to locate the buried channel as close as possible to the oxide as long as the minimum thickness for a low D-it is maintained. (C) 2002 Elsevier Science Ltd. All rights reserved.

引用

页码：1983 / 1989

页数：7

共 9 条

[1] Oxidation-induced traps near SiO2/SiGe interface [J].