Low voltage Stress-Induced-Leakage-Current in ultrathin gate oxides

被引：63

作者：

Nicollian, PE ^{[1
]}

Rodder, M ^{[1
]}

Grider, DT ^{[1
]}

Chen, PJ ^{[1
]}

Wallace, RM ^{[1
]}

Hattangady, SV ^{[1
]}

机构：

[1] Texas Instruments Inc, Silicon Technol Dev, Dallas, TX 75265 USA

来源：

1999 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 37TH ANNUAL | 1999年

关键词：

D O I：

10.1109/RELPHY.1999.761646

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Stress-Induced-Leakage-Current (SILC) is an important concern in ultrathin gate oxides because it may impose constraints on dielectric thickness scaling. We show that for oxides less than similar to 3.5 nm thick, interfacial traps generated from direct tunneling stress result in a sense voltage dependent SILC mechanism that can dominate the gate leakage current at low operating voltages.

引用

页码：400 / 404

页数：5

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