Electron and hole mobility enhancement in strained SOI by wafer bonding

被引：48

作者：

Huang, LJ ^{[1
]}

Chu, JO ^{[1
]}

Goma, SA ^{[1
]}

D'Emic, CP ^{[1
]}

Koester, SJ ^{[1
]}

Canaperi, DF ^{[1
]}

Mooney, PM ^{[1
]}

Cordes, SA ^{[1
]}

Speidell, JL ^{[1
]}

Anderson, RM ^{[1
]}

Wong, HSP ^{[1
]}

机构：

[1] IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2002年 / 49卷 / 09期

关键词：

CMOS; mobility; SiGe; silicon-on-insulator (SOI); strained silicon; wafer bending;

D O I：

10.1109/TED.2002.802675

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

N-and p-MOSFETs have been fabricated in strained Si-on-SiGe-on-insulator (SSOI) with high (15-25%) Ge content. Wafer bonding and H-induced layer transfer techniques enabled the fabrication of the high Ge content SiGe-on-insulator (SGOI) substrates. Mobility enhancement of 50% for electrons (with 15% Ge) and 15-20% for holes (with 20-25% Ge) has been demonstrated in SSOI MOSFETs. These mobility enhancements are commensurate with those reported for FETs fabricated on strained silicon on bulk SiGe substrates.

引用

页码：1566 / 1571

页数：6

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