A strategy for modeling of variations due to grain size in polycrystalline thin-film transistors

被引：52

作者：

Wang, AW ^{[1
]}

Saraswat, KC ^{[1
]}

机构：

[1] Stanford Univ, Ctr Integrated Syst, Stanford, CA 94305 USA

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2000年 / 47卷 / 05期

关键词：

flat panel displays; liquid crystal displays; Poisson distributions; polycrystalline; semiconductor defects; semiconductor device fabrication; semiconductor device modeling; semiconductor device manufacturing; semiconductor process modeling; silicon; statistics; thin-film transistors;

D O I：

10.1109/16.841238

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A strategy is presented for modeling of performance variation in polycrystalline thin-film transistors (TFT's) due to grain size variation. A Poisson area scatter is used to model the number of grains in a TFT, which is converted to grain size and substituted into physically based models for threshold and mobility. An increase in device variation is predicted as the device and grain sizes converge through scaling or process changes. Comparison of the model with measurements of NMOS TFT's results in reasonable agreement.

引用

页码：1035 / 1043

页数：9

共 29 条

[1] Modeling of laser-annealed polysilicon TFT characteristics [J].

Armstrong, GA ;

Uppal, S ;

Brotherton, SD ;

Ayres, JR .

IEEE ELECTRON DEVICE LETTERS, 1997, 18 (07) :315-318

[2] Deposition and characterization of polycrystalline silicon films on glass for thin film solar cells [J].

Bergmann, RB ;

Krinke, J ;

Strunk, HP ;

Werner, JH .

AMORPHOUS AND MICROCRYSTALLINE SILICON TECHNOLOGY - 1997, 1997, 467 :325-330

[3]

BRODY TP, 1992, P SOC PHOTO-OPT INS, V1664, P2, DOI 10.1117/12.60344

[4] EXCIMER-LASER-ANNEALED POLY-SI THIN-FILM TRANSISTORS [J].

BROTHERTON, SD ;

MCCULLOCH, DJ ;

CLEGG, JB ;

GOWERS, JP .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1993, 40 (02) :407-413

[5] AN ANALYTICAL MODEL FOR THE ABOVE-THRESHOLD CHARACTERISTICS OF POLYSILICON THIN-FILM TRANSISTORS [J].

CHERN, HN ;

LEE, CL ;

LEI, TF .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1995, 42 (07) :1240-1246

[6] Low-temperature single-crystal Si TFT's fabricated on Si films processed via sequential lateral solidification [J].

Crowder, MA ;

Carey, PG ;

Smith, PM ;

Sposili, RS ;

Cho, HS ;

Im, JS .

IEEE ELECTRON DEVICE LETTERS, 1998, 19 (08) :306-308

[7] Grain boundary potential barrier inhomogeneities in low-pressure chemical vapor deposited polycrystalline silicon thin-film transistors [J].

Dimitriadis, CA .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1997, 44 (09) :1563-1565

[8] On the threshold voltage and channel conductance of polycrystalline silicon thin-film transistors [J].

Dimitriadis, CA ;

Tassis, DH .

JOURNAL OF APPLIED PHYSICS, 1996, 79 (08) :4431-4437

[9] DETERMINATION OF GAP STATE DENSITY IN POLYCRYSTALLINE SILICON BY FIELD-EFFECT CONDUCTANCE [J].

FORTUNATO, G ;

MIGLIORATO, P .

APPLIED PHYSICS LETTERS, 1986, 49 (16) :1025-1027

[10] EFFECTS OF GRAIN-BOUNDARIES ON THE CHANNEL CONDUCTANCE OF SOI MOSFETS [J].

FOSSUM, JG ;

ORTIZCONDE, A .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1983, 30 (08) :933-940

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