Engineering on tunnel barrier and dot surface in Si nanocrystal memories

Nanocrystal memory is more scalable and operates under lower voltage than conventional floating gate memory thus it is currently a strong candidate for the next generation nonvolatile memory. However, those merits also raise critical problems on data retention and disturbance problems. Both problems are related to the sensitivity of the tunnel barrier on the applied field. When the field-sensitivity of the tunnel barrier becomes larger, both problems can be solved. One method is to increase the field-sensitivity of the tunnel barrier without increasing the operation voltage, which is profiling the band structure of the tunnel barrier. For example, barrier structure with a high bandgap sandwiched by two small bandgap dielectrics is a feasible one. We tried Si3N4/SiO2/Si3N4 barrier structure and observed the enhancement of the field sensitivity. In the experiment on the discharging kinetics, we could confirm the model of deep level charge storage. Moreover, it is related to the material that interfaces Si nanocrystals. The depth of energy level is higher when it is Si3N4 or amorphous carbon than when it is SiO7. Therefore, the choice of interface material on the dot surface should be considered based on the deep level formation for retention improvement. (C) 2004 Elsevier Ltd. All rights reserved.