Analysis of short-channel Schottky source/drain metal-oxide-semiconductor field-effect transistor on silicon-on-insulator substrate and demonstration of sub-50-nm n-type devices with metal gate

被引:73
作者
Saitoh, W [1 ]
Itoh, A [1 ]
Yamagami, S [1 ]
Asada, M [1 ]
机构
[1] Tokyo Inst Technol, Dept Elect & Elect Engn, Meguro Ku, Tokyo 1528552, Japan
来源
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS | 1999年 / 38卷 / 11期
关键词
Schottky source/drain MOSFET; short-channel device; SOI device; ErSi2/Si; metal gate;
D O I
10.1143/JJAP.38.6226
中图分类号
O59 [应用物理学];
学科分类号
摘要
The Schottky source/drain metal-oxide-semiconductor held-effect transistor (MOSFET) has potential for scaling to the nanometer regime, because low electrode resistances with very shallow extension can be realized using metal source/drain. In this study, very short channel n- and p-type Schottky source/drain MOSFETs with silicon-on-insulator (SOI) structure were analyzed theoretically, and n-type devices were demonstrated experimentally. It was shown theoretically that a drivability of the Schottky source/drain MOSFET comparable to that of conventional MOSFETs can be realized with a low Schottky barrier height. The short-channel effect can be suppressed even with a 15-nm-long channel at t(OX) = 1 nm and t(SOI) = 3 nm. The room-temperature operation of sub-50-nm n-type ErSi2 Schottky source/drain MOSFETs on a separation by implanted oxygen (SIMOX) substrate was demonstrated.
引用
收藏
页码:6226 / 6231
页数:6
相关论文
共 18 条
  • [1] ASHBURN SP, 1994, MATER RES SOC SYMP P, V320, P311
  • [2] A 7.9/5.5psec room/low temperature SOI CMOS
    Assaderaghi, F
    Rausch, W
    Ajmera, A
    Leobandung, E
    Schepis, D
    Wagner, L
    Wann, HJ
    Bolam, J
    Yee, D
    Davari, B
    Shahidi, G
    [J]. INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, : 415 - 418
  • [3] ASSADERAGHI F, 1994, INTERNATIONAL ELECTRON DEVICES MEETING 1994 - IEDM TECHNICAL DIGEST, P479, DOI 10.1109/IEDM.1994.383364
  • [4] SCALING THE MOS-TRANSISTOR BELOW 0.1 MU-M - METHODOLOGY, DEVICE STRUCTURES, AND TECHNOLOGY REQUIREMENTS
    FIEGNA, C
    IWAI, H
    WADA, T
    SAITO, M
    SANGIORGI, E
    RICCO, B
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1994, 41 (06) : 941 - 951
  • [5] Feasibility of using W/TiN as metal gate for conventional 0.13μm CMOS technology and beyond
    Hu, JC
    Yang, H
    Kraft, R
    Rotondaro, ALP
    Hattangady, S
    Lee, WW
    Chapman, RA
    Chao, CP
    Chatterjee, A
    Hanratty, M
    Rodder, M
    Chen, IC
    [J]. INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, : 825 - 828
  • [6] Two-dimensional numerical simulation of Schottky barrier MOSFET with channel length to 10 nm
    Huang, CK
    Zhang, WE
    Yang, CH
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1998, 45 (04) : 842 - 848
  • [7] Coulomb blockade oscillations at room temperature in a Si quantum wire metal-oxide-semiconductor field-effect transistor fabricated by anisotropic etching on a silicon-on-insulator substrate
    Ishikuro, H
    Fujii, T
    Saraya, T
    Hashiguchi, G
    Hiramoto, T
    Ikoma, T
    [J]. APPLIED PHYSICS LETTERS, 1996, 68 (25) : 3585 - 3587
  • [8] Interfacial reactions and electrical characteristics in Ti/SiGe/Si(100) contact systems
    Kojima, J
    Zaima, S
    Shinoda, H
    Iwano, H
    Ikeda, H
    Yasuda, Y
    [J]. APPLIED SURFACE SCIENCE, 1997, 117 : 317 - 320
  • [9] Reduction of the floating body effect in SOI MOSFETs by using Schottky source/drain contacts
    Nishisaka, M
    Asano, T
    [J]. JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1998, 37 (3B): : 1295 - 1299
  • [10] FIELD AND THERMIONIC-FIELD EMISSION IN SCHOTTKY BARRIERS
    PADOVANI, FA
    STRATTON, R
    [J]. SOLID-STATE ELECTRONICS, 1966, 9 (07) : 695 - &