Application-dependent scaling tradeoffs and optimization in the SoC era

被引：1

作者：

Díaz, CH ^{[1
]}

Chang, MC ^{[1
]}

Ong, TC ^{[1
]}

Sun, J ^{[1
]}

机构：

[1] Taiwan Semicond Mfg Co, Hsinchu, Taiwan

来源：

PROCEEDINGS OF THE IEEE 2002 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2002年

关键词：

D O I：

10.1109/CICC.2002.1012880

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Several physical phenomena in highly scaled CMOS technology have now become first order elements affecting electrical behavior of transistor characteristics. Effects such as STI mechanical stress, direct tunneling in gate dielectrics, gate line-edge roughness, and others, have significant influence on device characteristics. This paper elaborates on these effects to exemplify the need for closer interaction between circuit design and process development teams in order to push out application-dependent scaling limits. The paper also highlights the need for further efforts in the areas of circuit-level device modeling.

引用

页码：475 / 478

页数：4

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