A fully integrated 0.5-5.5-GHz CMOS distributed amplifier

A fully integrated 0.5-5.5-GHz CMOS-distributed amplifier is presented. The amplifier is a four-stage design fabricated in a standard 0.6-mu m three-layer metal digital-CMOS process. The amplifier has a unity-gain cutoff frequency of 5.5 GHz and again of 6.5 dB, with a gain flatness of +/-1.2 dB over the 0.5-4-GHz band, Input and output are matched to 50 Omega, with worst-case return losses on the input and output of -7 and -10 dB, respectively, Power dissipation is 83.4 mW from a 3.0-V supply, The input-referred 1-dB compression point varies from +6 dBm at 1 GHz to +8.8 dBm at 5 GHz, From a circuit standpoint, the fully integrated nature of the amplifier on the given substrate results in a heavily parasitic-laden design, Discussion emphasis is therefore placed on the practical design, modeling, and CAD optimization techniques used in the design process.