A p-channel MOS synapse transistor with self-convergent memory writes

被引:16
作者
Diorio, C [1 ]
机构
[1] Univ Washington, Dept Comp Sci & Engn, Seattle, WA 98195 USA
基金
美国国家科学基金会;
关键词
local learning; pFET; synapse transistor;
D O I
10.1109/16.822295
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We have developed a p-channel floating-gate-MOS synapse transistor for silicon-learning applications, The synapse stores a nonvolatile analog weight by means of charge on its floating gate, modifies this weight bidirectionally using electron tunneling and hot-electron injection, and allows simultaneous memory reading and writing. The synapse also learns locally-its weight updates depend only on the applied terminal voltages and on the stored weight, We fabricated an array of synapses that computed both the array output, and the weight updates, in parallel. We also demonstrated a self-convergent write procedure that permitted accurate initialization of the synapse weights. Our pFET synapse is small, and is operated at subthreshold current levels; it will permit the development of dense, low-power, silicon learning systems.
引用
收藏
页码:464 / 472
页数:9
相关论文
共 20 条
[1]  
ANDREOU AG, 1994, ANALOG VLSI SIGNAL I, P358
[2]   RELIABILITY ISSUES OF FLASH MEMORY CELLS [J].
ARITOME, S ;
SHIROTA, R ;
HEMINK, G ;
ENDOH, T ;
MASUOKA, F .
PROCEEDINGS OF THE IEEE, 1993, 81 (05) :776-788
[3]   CONDUCTANCE MECHANISM RESPONSIBLE FOR LONG-TERM POTENTIATION IN MONO-SYNAPTIC AND ISOLATED EXCITATORY SYNAPTIC INPUTS TO HIPPOCAMPUS [J].
BARRIONUEVO, G ;
KELSO, SR ;
JOHNSTON, D ;
BROWN, TH .
JOURNAL OF NEUROPHYSIOLOGY, 1986, 55 (03) :540-550
[4]   A 4-STATE EEPROM USING FLOATING-GATE MEMORY CELLS [J].
BLEIKER, C ;
MELCHIOR, H .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (03) :460-463
[5]   Performance and reliability evaluations of P-channel flash memories with different programming schemes [J].
Chung, SS ;
Kuo, SN ;
Yih, CM ;
Chao, TS .
INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, :295-298
[6]  
Churchland P. S., 1993, The Computational Brain
[7]   A single-transistor silicon synapse [J].
Diorio, C ;
Hasler, P ;
Minch, A ;
Mead, CA .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1996, 43 (11) :1972-1980
[8]   A complementary pair of four-terminal silicon synapses [J].
Diorio, C ;
Hasler, P ;
Minch, BA ;
Mead, C .
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 1997, 13 (1-2) :153-166
[9]  
Diorio C, 1998, ANALOG CIRCUITS SIG, P315
[10]  
DIORIO C, 1997, Patent No. 5627392