Effects of selecting channel direction in improving performance of sub-100nm MOSFETs fabricated on (110) surface Si substrate

被引：17

作者：

Nakamura, H

Ezaki, T

Iwamoto, T

Togo, M

Ikezawa, T

Ikarashi, N

Hane, M

Yamamoto, T

机构：

[1] NEC Corp Ltd, Silicon Syst Res Labs, Sagamihara, Kanagawa 2291198, Japan

[2] NEC Informatec Syst Ltd, Platform Software Div, Takatsu Ku, Kawasaki, Kanagawa 2130012, Japan

来源：

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS | 2004年 / 43卷 / 4B期

关键词：

MOSFET; (110) surface Si substrate; mobility; channel direction; surface roughness; channeling; short channel characteristics; CMOS performance;

D O I：

10.1143/JJAP.43.1723

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

We investigated the low field mobility and short channel characteristics of metal-oxide-semiconductor field-effect transistors (MOSFETs) on (110) surface Si substrates with various channel directions from the viewpoints of experiment and numerical simulation. We found that the mobility (mu) ratio of (110) substrates to (001) substrates (mu((110))/mu((001))) does not depend on the vertical electric field due to the identical surface roughness for (110) and (001) substrates. We verified mobility enhancement and its channel direction dependence by conducting a detailed carrier transport simulation using a full band model and relaxation time approximation. We obtained good threshold voltage (V-th) lowering characteristics due to the suppression of channeling at the source and drain (SD) extension by implant sequence control. Our results showed that the improvement in propagation delay time (CV/I) and on-current ratio of nMOS to pMOS (I-on(n)/I-on(p)) obtained by using an optimized combination of channel directions and a ( I 10) surface Si substrate is attractive for future LSIs down to the sub-100 nm region.

引用

页码：1723 / 1728

页数：6

共 18 条

[1]

EZAKI T, UNPUB J COMP ELECT

[2] MONTE-CARLO STUDY OF ELECTRON-TRANSPORT IN SILICON INVERSION-LAYERS [J].

FISCHETTI, MV ;

LAUX, SE .

PHYSICAL REVIEW B, 1993, 48 (04) :2244-2274

[3] Modeling of ultra-low energy boron implantation in silicon [J].

Hobler, G ;

Vuong, HH ;

Bevk, J ;

Agarwal, A ;

Gossmann, HJ ;

Foad, M ;

Murrell, A ;

Erokhin, Y .

INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, :489-492

[4]

Hoyt JL, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P23, DOI 10.1109/IEDM.2002.1175770

[5] CMOS device optimization for system-on-a-chip applications [J].

Imai, K ;

Yamaguchi, K ;

Kudo, T ;

Kimizuka, N ;

Onishi, H ;

Ono, A ;

Nakahara, Y ;

Goto, Y ;

Noda, K ;

Masuoka, S ;

Ito, S ;

Matsui, K ;

Ando, K ;

Ohashi, EHT ;

Oda, N ;

Yokoyama, K ;

Takewaki, T ;

Sone, S ;

Horiuchi, T .

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, :455-458

[6] On the mobility versus drain current relation for a nanoscale MOSFET [J].

Lundstrom, MS .

IEEE ELECTRON DEVICE LETTERS, 2001, 22 (06) :293-295

[7]

Matsumoto T, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P663, DOI 10.1109/IEDM.2002.1175926

[8]

MOMOSE HS, 2002 S VLSI TECH, P156

[9]

Nakatsuji H, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P727, DOI 10.1109/IEDM.2002.1175941

[10] Nonstationary electron/hole transport in sub-0.1 μm MOS devices:: Correlation with mobility and low-power CMOS application [J].

Ohba, R ;

Mizuno, T .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2001, 48 (02) :338-343

← 1 2 →