New route to zero-barrier metal source/drain MOSFETs

被引：104

作者：

Connelly, D ^{[1
]}

Faulkner, C

Grupp, DE

Harris, JS

机构：

[1] Acorn Technol, Palo Alto, CA 94036 USA

[2] Stanford Univ, Stanford, CA 94035 USA

来源：

IEEE TRANSACTIONS ON NANOTECHNOLOGY | 2004年 / 3卷 / 01期

关键词：

nanotechnology; Schottky barriers; Schottky diodes; Schottky logic circuits; Schottky logic devices; silicon-on-insulator (SOI) technology;

D O I：

10.1109/TNANO.2003.820774

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new method for dramatically lowering the Schottky barrier resistance at a metal/Si interface by interposing an ultrathin insulator is demonstrated for the first time, with thermionic barriers less than those reported to date with silicides. Results with Er and near-monolayer thermal SiNx at the interface are consistent with simulations of effective metal Fermi level separations from the silicon conduction band of 0.15 V for n-type Si and 45 mV for p-type Si. Simulations of advanced metal source/drain (S/D) ultrathin-body CMOS devices in comparison with competitive doped S/D devices show a significant performance advantage with a barrier to the conduction band of up to 0.1 V.

引用

页码：98 / 104

页数：7

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