Optimizing Schottky S/D offset for 25-nm dual-gate CMOS performance

被引：34

作者：

Connelly, D ^{[1
]}

Faulkner, C ^{[1
]}

Grupp, DE ^{[1
]}

机构：

[1] Acorn Technol, Palo Alto, CA 94061 USA

来源：

IEEE ELECTRON DEVICE LETTERS | 2003年 / 24卷 / 06期

关键词：

CMOSFET circuits; MOS devices; Schottky barriers; semiconductor device modeling; semiconductor-metal interfaces; silicon; silicon on insulator technology; simulation;

D O I：

10.1109/LED.2003.813363

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

For the first time,mixed mode simulation is used to optimize the design of ultrathin-body dual-gate metal source/drain 25-nm CMOS, showing an advantage for source/drain-to-gate underlap, rather than overlap. The effect of source/drain work-function and silicon thickness on the optimal underlap, and on the resulting circuit speed, is examined. A substantial performance advantage versus doped source/drain is demonstrated.

引用

收藏

页码：411 / 413

页数：3

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