共 20 条
[1]
[Anonymous], 1999, INT TECHNOLOGY ROADM
[2]
Antoniadis D.A., 1999, MIT Well Tempered Bulk-Si NMOSFET Device
[3]
Axelrad V, 2000, 2000 INTERNATIONAL CONFERENCE ON ION IMPLANTATION TECHNOLOGY, PROCEEDINGS, P239, DOI 10.1109/IIT.2000.924134
[4]
Improved device technology evaluation and optimization
[J].
2000 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES,
2000,
:155-158
[5]
Anomalous short-channel effects in 0.1 mu m MOSFETs
[J].
IEDM - INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST 1996,
1996,
:571-574
[7]
Felch SB, 2000, 2000 INTERNATIONAL CONFERENCE ON ION IMPLANTATION TECHNOLOGY, PROCEEDINGS, P167, DOI 10.1109/IIT.2000.924116
[8]
Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors
[J].
2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS,
2000,
:174-175
[9]
A study of ultra shallow junction and tilted channel implantation for high performance 0.1μm pMOSFETs
[J].
INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST,
1998,
:631-634