The impact of gate-oxide breakdown on SRAM stability

被引：99

作者：

Rodríguez, R

Stathis, JH

Linder, BP

Kowalczyk, S

Chuang, CT

Joshi, RV

Northrop, G

Bernstein, K

Bhavnagarwala, AJ

Lombardo, S

机构：

[1] Univ Autonoma Barcelona, Dept Elect Engn, Bellaterra 08193, Spain

[2] IBM Corp, Div Res, Yorktown Hts, NY 10598 USA

[3] IBM Microelect, Essex Jct, VT 05452 USA

[4] CNR, IMTEM, I-95121 Catania, Italy

来源：

IEEE ELECTRON DEVICE LETTERS | 2002年 / 23卷 / 09期

关键词：

dielectric breakdown; hard breakdown; leakage currents; MOS devices; oxide reliability; soft breakdown; SRAM;

D O I：

10.1109/LED.2002.802600

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have investigated the effects of oxide soft breakdown (SBD) on the stability of CMOS 6T SRAM cells. Gate-to-diffusion leakage currents of 20-50 muA at the n-FET source can result in a 50% reduction of noise margin. Breakdown at other locations in the cell may be less deleterious depending on n-FET width. This approach gives targets for tolerable values of leakage caused by gate-oxide breakdown.

引用

页码：559 / 561

页数：3

共 10 条

[1] The impact of intrinsic device fluctuations on CMOS SRAM cell stability [J].

Bhavnagarwala, AJ ;

Tang, XH ;

Meindl, JD .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (04) :658-665

[2] Reliability: a possible showstopper for oxide thickness scaling? [J].

Degraeve, R ;

Kaczer, B ;

Groeseneken, G .

SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2000, 15 (05) :436-444

[3] High-performance sub-0.08 μm CMOS with dual gate oxide and 9.7 ps inverter delay [J].

Hargrove, M ;

Crowder, S ;

Nowak, E ;

Logan, R ;

Han, LK ;

Ng, H ;

Ray, A ;

Sinitsky, D ;

Smeys, P ;

Guarin, F ;

Oberschmidt, J ;

Crabbé, E ;

Yee, D ;

Su, L .

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, :627-630

[4] Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM [J].

Joshi, RV ;

Chuang, CT ;

Fung, SKH ;

Assaderaghi, F ;

Sherony, M ;

Yang, I ;

Shahidi, G .

2001 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2001, :75-76

[5] Impact of MOSFET oxide breakdown on digital circuit operation and reliability [J].

Kaczer, B ;

Degraeve, R ;

Groeseneken, G ;

Rasras, M ;

Kubicek, S ;

Vandamme, E ;

Badenes, G .

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, :553-556

[6] A function-fit model for the soft breakdown failure mode [J].

Miranda, E ;

Suñé, J ;

Rodríguez, R ;

Nafría, M ;

Aymerich, X .

IEEE ELECTRON DEVICE LETTERS, 1999, 20 (06) :265-267

[7] STATIC-NOISE MARGIN ANALYSIS OF MOS SRAM CELLS [J].

SEEVINCK, E ;

LIST, FJ ;

LOHSTROH, J .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (05) :748-754

[8] A detailed analysis of CMOS SRAM's with gate oxide short defects [J].

Segura, J ;

Rubio, A .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (10) :1543-1550

[9] A high performance 0.13μm SOICMOS technology with Cu interconnects and low-k BEOL dielectric [J].

Smeys, P ;

McGahay, V ;

Yang, I ;

Adkisson, J ;

Beyer, K ;

Bula, O ;

Chen, Z ;

Chu, B ;

Culp, J ;

Das, S ;

Eckert, A ;

Hadel, L ;

Hargrove, M ;

Herman, J ;

Lin, L ;

Mann, R ;

Maciejewski, E ;

Narasimha, S ;

O'Neill, P ;

Rauch, S ;

Ryan, D ;

Toomey, J ;

Tsou, L ;

Varekamp, P ;

Wachnik, R ;

Wagner, T ;

Wu, S ;

Yu, C ;

Agnello, P ;

Connolly, J ;

Crowder, S ;

Davis, C ;

Ferguson, R ;

Sekiguchi, A ;

Su, L ;

Goldblatt, R ;

Chen, TC .

2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2000, :184-185

[10] Reliability projection for ultra-thin oxides at low voltage [J].

Stathis, JH ;

DiMaria, DJ .

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, :167-170

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