A closed-form back-gate-bias related inverse narrow-channel effect model for deep-submicron VLSI CMOS devices using shallow trench isolation

被引：16

作者：

Lin, SC ^{[1
]}

Kuo, JB

Huang, KT

Sun, SW

机构：

[1] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan

[2] United Microelectron Corp, Adv Technol Dept, Hsinchu, Taiwan

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2000年 / 47卷 / 04期

关键词：

conformal mapping technique; inverse narrow-channel effect; small geometry; STI;

D O I：

10.1109/16.830986

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper reports an analytical inverse narrow-channel effect threshold voltage model for shallow-trench-isolated (STI) CMOS devices using a conformal mapping technique to simplify the two-dimensional (2-D) analysis, As verified by the experimentally measured data and the 2-D simulation results, the analytical model predicts well the inverse narrow-channel effect threshold voltage behavior of the STI CMOS devices, Based on the study, the inverse narrow-channel effect also affects the saturation-region output conductance of a small-geometry STI CMOS device in addition to the short-channel effect.

引用

页码：725 / 733

页数：9

共 15 条

[1] CHARACTERIZATION OF THE INVERSE-NARROW-WIDTH EFFECT [J].

AKERS, LA ;

SUGINO, M ;

FORD, JM .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1987, 34 (12) :2476-2484

[2]

CHATTERJEE A, 1996, VLSI TECH, P156

[3] A novel 0.25 mu m shallow trench isolation technology [J].

Chen, C ;

Chou, JW ;

Lur, W ;

Sun, SW .

IEDM - INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST 1996, 1996, :837-840

[4] AN ANALYTICAL DRAIN CURRENT MODEL CONSIDERING BOTH ELECTRON AND LATTICE TEMPERATURES SIMULTANEOUSLY FOR DEEP-SUBMICRON ULTRATHIN SOI NMOS DEVICES WITH SELF-HEATING [J].

CHEN, YG ;

MA, SY ;

KUO, JB ;

YU, ZP ;

DUTTON, RW .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1995, 42 (05) :899-906

[5] AN ANALYTICAL THRESHOLD-VOLTAGE MODEL OF TRENCH-ISOLATED MOS DEVICES WITH NONUNIFORMLY DOPED SUBSTRATES [J].

CHUNG, SSS ;

LI, TC .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1992, 39 (03) :614-622

[6] AN ANALYTICAL MODEL FOR THE INVERSE NARROW-GATE EFFECT OF A METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR [J].

HONG, KM ;

CHENG, YC .

JOURNAL OF APPLIED PHYSICS, 1987, 61 (06) :2387-2392

[7] INVERSE-NARROW-WIDTH EFFECTS AND SMALL-GEOMETRY MOSFET THRESHOLD VOLTAGE MODEL [J].

HSUEH, KKL ;

SANCHEZ, JJ ;

DEMASSA, TA ;

AKERS, LA .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1988, 35 (03) :325-338

[8]

LEE HS, 1996, VLSI TECH DIG, P158

[9] Analytical subthreshold current hump model for deep-submicron shallow-trench-isolated CMOS devices [J].

Lin, SC ;

Kuo, JB ;

Huang, KT ;

Sun, SW .

SOLID-STATE ELECTRONICS, 1998, 42 (10) :1871-1879

[10]

*MEDICI, 1996, 2 DIM DEV SIM PROGR

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