Low energy BF2 implantation for the suppression of B penetration

In sub-quarter micron p(+) gate pMOS fabrication, the crucial problem is the boron penetration through the thin gate oxide to the Si substrate. In BF2 implantation for source/drain and gate polysilicon, boron penetration is caused by fluorine piling up at the gate oxide, which induces enhanced diffusion of boron. However, no details have been reported on fluorine profiles at the interface of gate polysilicon/gate oxide layers. This paper shows that fluorine piled up at the gate oxide is strongly dependent on the BF2 implantation energy, and that B penetration through the gate oxide can be suppressed by BF2 implantation at 3 keV, because of the reduction of fluorine concentration at the gate oxide, This technique can be used to fabricate 0.15-mu m pMOS devices.