On the performance limits for Si MOSFET's: A theoretical study

被引:168
作者
Assad, F [1 ]
Ren, ZB
Vasileska, D
Datta, S
Lundstrom, M
机构
[1] Purdue Univ, Sch Elect & Comp Engn, W Lafayette, IN 47907 USA
[2] Arizona State Univ, Dept Elect Engn, Tempe, AZ 85287 USA
基金
美国国家科学基金会;
关键词
charge carrier processes; MOSFET's; nanotechnology; semiconductor device modeling; semiconductor devices;
D O I
10.1109/16.817590
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Performance limits of silicon MOSFET's are examined by a simple analytical theory augmented by self-consistent Schrodinger-Poisson simulations, The on-current, transconductance, and drain-to-source resistance in the ballistic limit (which corresponds to the channel length approaching zero) are examined. The ballistic transconductance in the limit that the oxide thickness approaches zero is also examined. The results show that as the channel length approaches zero (which corresponds to the ballistic limit), the on-current and transconductance approach finite limiting values and the channel resistance approaches a finite minimum value, The source velocity can be as high as about 1.5 x 10(7) cm/s. The limiting on-current and transconductance are considerably higher than those deduced experimentally by a previous study of MOSFET's with channel lengths greater than 0.2 mu m. At the same time, the transconductance to current ratio is substantially lower than that of a bipolar transistor.
引用
收藏
页码:232 / 240
页数:9
相关论文
共 17 条
[11]   BALLISTIC METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR [J].
NATORI, K .
JOURNAL OF APPLIED PHYSICS, 1994, 76 (08) :4879-4890
[12]   DESIGN AND EXPERIMENTAL TECHNOLOGY FOR 0.1-MU-M GATE-LENGTH LOW-TEMPERATURE OPERATION FETS [J].
SAIHALASZ, GA ;
WORDEMAN, MR ;
KERN, DP ;
GANIN, E ;
RISHTON, S ;
ZICHERMAN, DS ;
SCHMID, H ;
POLCARI, MR ;
NG, HY ;
RESTLE, PJ ;
CHANG, THP ;
DENNARD, RH .
IEEE ELECTRON DEVICE LETTERS, 1987, 8 (10) :463-466
[13]  
*SEM IND ASS, 1997, NAT TECHN ROADM SEM
[14]   INDIUM CHANNEL IMPLANT FOR IMPROVED SHORT-CHANNEL BEHAVIOR OF SUBMICROMETER NMOSFETS [J].
SHAHIDI, GG ;
DAVARI, B ;
BUCELOT, TJ ;
RONSHEIM, PA ;
COANE, PJ ;
POLLACK, S ;
BLAIR, CR ;
CLARK, B ;
HANSEN, HH .
IEEE ELECTRON DEVICE LETTERS, 1993, 14 (08) :409-411
[15]  
TIMP G, 1997, IEDM WASH DC DEC
[16]   ON THE PERFORMANCE LIMIT FOR SI MOSFETS - EXPERIMENTAL-STUDY [J].
TORIUMI, A ;
IWASE, M ;
YOSHIMI, M .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1988, 35 (07) :999-1003
[17]   Scaled silicon MOSFET's: Degradation of the total gate capacitance [J].
Vasileska, D ;
Schroder, DK ;
Ferry, DK .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1997, 44 (04) :584-587