Investigation of Cu/TaN metal gate for metal-oxide-silicon devices

被引:10
作者
Tsui, BY [1 ]
Huang, CF
机构
[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu, Taiwan
[2] Natl Chiao Tung Univ, Inst Elect, Hsinchu 30039, Taiwan
关键词
D O I
10.1149/1.1522723
中图分类号
O646 [电化学、电解、磁化学];
学科分类号
081704 ;
摘要
This work investigates the work function modulation of TaNx films and the thermal stability of Cu/TaNx stack as a gate electrode for metal-oxide-silicon devices. The N/Ta ratio was varied in the range of 0.30-0.65 by using reactive-sputter deposition with various Ar/N-2 mass flow ratios. The TaNx films are almost amorphous and are thermally stable up to 800degreesC. However, the formation of Ta3N5 phase in a film with a high N/Ta ratio or annealed at high temperature increases the resistivity. The work function of TaNx is about 4.31-4.38 eV and the modulation is less than 70 mV. Such a short range modulation of the work function implies that TaNx is only suitable to be a gate electrode of surface channel n-channel metal oxide semiconductor field effect transistors (NMOSFETs). The mean value of the flatband voltage decreases and the deviation of the flatland voltage increases with the increase of the annealing temperature. Although phase change, grain growth, and Cu contamination contribute to the instability at high temperature, thermal stress-induced oxide charges dominate this decrease and deviation of the flatband voltage at temperature below 500degreesC. According to the material and electrical analysis, the Cu/TaNx stack gate electrode can be used for NMOSFETs only, and the maximum process temperature following gate electrode deposition should be lower than 500degreesC. (C) 2002 The Electrochemical Society.
引用
收藏
页码:G22 / G27
页数:6
相关论文
共 28 条
[21]  
Suh YS, 2001, 2001 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P47, DOI 10.1109/VLSIT.2001.934940
[22]  
Sze S M, 1981, PHYSICS SEMICONDUCTO, P368
[23]  
Tsui BY, 1996, 1996 1ST INTERNATIONAL SYMPOSIUM ON PLASMA PROCESS-INDUCED DAMAGE, P148
[24]   A high performance 1.8V, 0.20μm CMOS technology with copper metallization [J].
Venkatesan, S ;
Gelatos, AV ;
Misra, V ;
Smith, B ;
Islam, R ;
Cope, J ;
Wilson, B ;
Tuttle, D ;
Cardwell, R ;
Anderson, S ;
Angyal, M ;
Bajaj, R ;
Capasso, C ;
Crabtree, P ;
Das, S ;
Farkas, J ;
Filipiak, S ;
Fiordalice, B ;
Freeman, M ;
Gilbert, PV ;
Herrick, M ;
Jain, A ;
Kawasaki, H ;
King, C ;
Klein, J ;
Lii, T ;
Reid, K ;
Saaranen, T ;
Simpson, C ;
Sparks, T ;
Tsui, P ;
Venkatraman, R ;
Watts, D ;
Weitzman, EJ ;
Woodruff, R ;
Yang, I ;
Bhat, N ;
Hamilton, G ;
Yu, Y .
INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, :769-772
[25]  
Wakabayashi H., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P253, DOI 10.1109/IEDM.1999.823891
[26]   High performance metal gate MOSFETs fabricated by CMP for 0.1μm regime [J].
Yagishita, A ;
Saito, T ;
Nakajima, K ;
Inumiya, S ;
Akasaka, Y ;
Ozawa, Y ;
Minamihaba, G ;
Yano, H ;
Hieda, K ;
Suguro, K ;
Arikado, T ;
Okumura, A .
INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, :785-788
[27]   Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric [J].
Yeo, YC ;
Lu, Q ;
Ranade, P ;
Takeuchi, H ;
Yang, KJ ;
Polishchuk, I ;
King, TJ ;
Hu, C ;
Song, SC ;
Luan, HF ;
Kwong, DL .
IEEE ELECTRON DEVICE LETTERS, 2001, 22 (05) :227-229
[28]  
Yu B, 1997, 1997 SYMPOSIUM ON VLSI TECHNOLOGY, P105, DOI 10.1109/VLSIT.1997.623717