Performance estimation of Si/SiGe hetero-CMOS circuits

被引：18

作者：

Hagelauer, R

Ostermann, T

Konig, U

Gluck, M

Hock, G

机构：

[1] DAIMLER BENZ AG,ULM RES CTR,D-89081 ULM,GERMANY

[2] UNIV ULM,DEPT ELECTRON DEVICES & CIRCUITS,D-89069 ULM,GERMANY

来源：

ELECTRONICS LETTERS | 1997年 / 33卷 / 03期

关键词：

silicon; silicon-germanium; CMOS integrated circuits;

D O I：

10.1049/el:19970166

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Semiquantitative performance extrapolation heterostructure p- and n-channel devices point conductances above 1000mS/mm and cutoff frequencies around 200GHz. Circuits such as inverters, logic arrays (e.g. NAND-gates) and flip-flops are simulated with feature sizes down to 0.05 mu m showing a promising performance potential. Delay times of 2.5 and 0.5ps/stage are obtained for an inverter chain at a power supply voltage of 1 and 2.5V, respectively.

引用

收藏

页码：208 / 210

页数：3

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