Highly reliable PVD/ALD/PVD stacked barrier metal structure for 45nm-node copper dual-damascene interconnects

被引：17

作者：

Higashi, K ^{[1
]}

Yamaguchi, H ^{[1
]}

Omoto, S ^{[1
]}

Sakata, A ^{[1
]}

Katata, T ^{[1
]}

Matsunaga, N ^{[1
]}

Shibata, H ^{[1
]}

机构：

[1] Toshiba Co Ltd, Semicond Co, Syst LSI Res & Dev Ctr, Isogo Ku, Yokohama, Kanagawa 2358522, Japan

来源：

PROCEEDINGS OF THE IEEE 2004 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2004年

关键词：

D O I：

10.1109/IITC.2004.1345664

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we describe highly reliable barrier metal structure for 45nm node (140nm pitch) high performance copper interconnects. Issues and solutions for utilizing TaN barrier metal by atomic-layer deposition (ALD) process, which is the key technology for scaling down the barrier metal thickness, on low-k ILD materials were investigated. PVD/ALD/PVD stacked barrier metal structure was proposed from the viewpoint of factors affecting reliability such as stress-induced voiding (SiV) and electromigration (EM) endurance, and realized lower wiring resistance than that is attainable with the conventional process. We distinguished the role of each PVD film, and suggest the optimal barrier metal structure to realize highly reliable Cu dual-damascene interconnects.

引用

页码：6 / 8

页数：3

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