Dynamic-threshold CMOS SRAM cells for fast, portable applications

被引：16

作者：

Bhavnagarwala, AJ ^{[1
]}

Kapoor, A ^{[1
]}

Meindl, JD ^{[1
]}

机构：

[1] Georgia Inst Technol, Microelect Res Ctr, Atlanta, GA 30332 USA

来源：

13TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS | 2000年

关键词：

D O I：

10.1109/ASIC.2000.880764

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A novel quad-rail CMOS SRAM cell architecture that doubles cell read current, improves cell static noise margin (SNM) by 70%, increases cell immunity to SER and lowers cell standby power by over an order of magnitude is proposed. These improvements are achieved by implementing a scheme of WL transition triggered pulses on source and substrate terminals of cell inverter transistors that share a common WL.

引用

页码：359 / 363

页数：5

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