共 4 条
Evaluation of 0.3 μm poly-silicon CMOS circuits for intelligent power IC application
被引:6
作者:
Matsudai, T
[1
]
Terauchi, M
[1
]
Yoshimi, M
[1
]
Yasuhara, N
[1
]
Ushiku, Y
[1
]
Nakagawa, A
[1
]
机构:
[1] Toshiba Corp, Adv Semicond Devices Res Labs, Saiwai Ku, Kawasaki, Kanagawa 210, Japan
来源:
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS
|
1998年
/
37卷
/
3B期
关键词:
polysilicon;
CMOS;
power IC;
fine device;
amorphous silicon;
recrystallization;
NAND ring;
delay time;
D O I:
10.1143/JJAP.37.1103
中图分类号:
O59 [应用物理学];
学科分类号:
摘要:
In this paper, we report on The fine device performance of a 0.3 mu m gate length polysilicon complementary metaloxide-semiconductor (CMOS). The breakdown voltage of 0.3 mu m n-channel metal-oxide-semiconductor field effect transistor (NMOSFET) devices exceeds 6 V, which is higher than that of NMOSFET devices on separation by implanted oxygen (SIMOX) wafer. The drain current of a 10 mu m channel width device is 540 mu A, which is one-fifth of that of NMOSFET on SIMOX. The leakage current is less than 10(-11) A/mu m, when the gate voltage is below 0 V. The S-factor is 125 mV/dec, and the threshold voltage is 0.4 V. Therefore the ON/OFF current ratio is greater than 10(7). A delay time of 1 ns is achieved in polysilicon NAND rings. Hence, it is ascertained that the polysilicon CMOS is applicable for the fabrication of control and protection circuits on power devices.
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页码:1103 / 1106
页数:4
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