Energy-efficient low-voltage operation of digital CMOS circuits through charge-recycling

被引:10
作者
Rajapandian, S [1 ]
Xu, Z [1 ]
Shepard, KL [1 ]
机构
[1] Columbia Univ, Dept Elect Engn, Columbia Integrated Syst Lab, New York, NY 10027 USA
来源
2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2004年
关键词
D O I
10.1109/VLSIC.2004.1346605
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper describes an energy-efficient means to achieve on-chip dc-dc conversion for digital CMOS circuits. The approach uses balanced voltage islands running at fractions of the off-chip supply voltage. Charge "discarded" by one domain is "recycled" to supply energy for another. When the domains are ideally balanced, all the energy dissipated by electrons in "dropping" to lower potentials is used for active computation. We describe the design and measurement of a prototype system in a 0.18 mum CMOS process that provides active on-chip voltage regulation and controlled dc-dc conversion with this technique.
引用
收藏
页码:330 / 333
页数:4
相关论文
共 11 条
[1]  
Burd T, 2000, INT S LOW POW EL DES
[2]   Dual-threshold voltage techniques for low-power digital circuits [J].
Kao, JT ;
Chandrakasan, AP .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (07) :1009-1018
[3]   Managing power and performance for System-on-Chip designs using voltage islands [J].
Lackey, DE ;
Zuchowski, PS ;
Bednar, TR ;
Stout, DW ;
Gould, SW ;
Cohn, JM .
IEEE/ACM INTERNATIONAL CONFERENCE ON CAD-02, DIGEST OF TECHNICAL PAPERS, 2002, :195-202
[4]  
PATOUNAKIS G, 2004, IEEE J SOLID STA MAR
[5]  
QU G, 1999, P IEEE INT S CIRC SY
[6]   Charge-recycling voltage domains for energy-efficient low-voltage operation of digital CMOS circuits [J].
Rajapandian, S ;
Xu, Z ;
Shepard, KL .
21ST INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, PROCEEDINGS, 2003, :98-102
[7]  
SEMERARO G, 2002, P INT S HIGH PERF CO
[8]  
USAMI K, 1995, P WORKSH LOW POW DES
[9]  
WEI GY, 2000, IEEE J SOLID-ST CIRC, P520
[10]   AN ASYMPTOTICALLY ZERO POWER CHARGE-RECYCLING BUS ARCHITECTURE FOR BATTERY-OPERATED ULTRAHIGH DATA RATE ULSIS [J].
YAMAUCHI, H ;
AKAMATSU, H ;
FUJITA, T .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1995, 30 (04) :423-431