Ge deep sub-micron pFETs with etched TaN metal gate on a High-K dielectric, fabricated in a 200mm silicon prototyping line

被引：19

作者：

De Jaeger, B ^{[1
]}

Houssa, M ^{[1
]}

Satta, A ^{[1
]}

Kubicek, S ^{[1
]}

Verheyen, P ^{[1
]}

Van Steenbergen, J ^{[1
]}

Croon, J ^{[1
]}

Kaczer, B ^{[1
]}

Van Elshocht, S ^{[1
]}

Delabie, A ^{[1
]}

Kunnen, E ^{[1
]}

Sleeckx, E ^{[1
]}

Teerlinck, I ^{[1
]}

Lindsay, R ^{[1
]}

Schram, T ^{[1
]}

Chiarella, T ^{[1
]}

Degraeve, R ^{[1
]}

Conard, T ^{[1
]}

Poortmans, J ^{[1
]}

Winderickx, G ^{[1
]}

Boullart, W ^{[1
]}

Schaekers, M ^{[1
]}

Mertens, PW ^{[1
]}

Caymax, M ^{[1
]}

Vandervorst, W ^{[1
]}

Van Moorhem, E ^{[1
]}

Biesemans, S ^{[1
]}

De Meyer, K ^{[1
]}

Ragnarsson, L ^{[1
]}

Lee, S ^{[1
]}

Kota, G ^{[1
]}

Raskin, G ^{[1
]}

Mijlemans, P ^{[1
]}

Autran, JL ^{[1
]}

Afanas'ev, VV ^{[1
]}

Stesmans, A ^{[1
]}

Meuris, M ^{[1
]}

Heyns, M ^{[1
]}

机构：

[1] IMEC, B-3001 Louvain, Belgium

来源：

ESSDERC 2004: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2004年

关键词：

D O I：

10.1109/ESSDER.2004.1356521

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report for the first time on deep sub-micron Ge pFETs with physical gate lengths down to 0.15 mum. The devices are made using a silicon-like process flow, with a directly etched gate stack consisting of TaN gate on an ALD or MOCVD HfO2 dielectric. Promising drive currents are found. Various issues such as the severe short channel effects (SCE), the increased diode leakage compared to Si and the high amount of interface states (N-it) are addressed. The need for an alternative Ge substrate pre-treatment and subsequent High-K gate dielectric deposition to push EOT values below 1nm is illustrated.

引用

页码：189 / 192

页数：4

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