Interface trap generation and hole trapping under NBTI and PBTI in advanced CMOS technology with a 2-nm gate oxide

This paper gives an insight into the degradation mechanisms during negative and positive bias temperature instabilities in advanced CMOS technology with a 2-nn gate oxide: We focus on generated interface traps and oxide traps to distinguish their dependencies and effects on usual transistor parameters. negative bias temperature instability (NBTI) and positive bias temperature instability-in both NMOS and PMOS have been compared and a possible explanation for all configurations has been suggested. Recovery. and temperature effect under NBTI were also. investigated showing different behaviors of the two components.