Fabrication of nanometer-scale vertical metal-insulator-metal tunnel junctions using a silicon-on-insulator substrate

被引:3
作者
Haraichi, S [1 ]
Wada, T [1 ]
Gorwadkar, SM [1 ]
Ishii, K [1 ]
机构
[1] Electrotech Lab, Tsukuba, Ibaraki 305, Japan
来源
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS | 1998年 / 37卷 / 3B期
关键词
metal-insulator-metal tunnel junction; Coulomb staircase; electron beam lithography; inorganic resist; nanofabrication;
D O I
10.1143/JJAP.37.1580
中图分类号
O59 [应用物理学];
学科分类号
摘要
We have developed a vertical metal-insulator-metal (MIM) junctions fabrication process using a silicon on insulator (SOI) substrate. The diameter of the contact-hole of the top SiO2 layer tends to saturate with an increase in exposed dose, and a mask with a contact-hole of a minimum diameter of about 15 nm was successfully fabricated. An aluminum vertical array of two MIM junctions exhibited the typical current-voltage (I-V) characteristics of tunnel junctions at room temperature. However, they showed a large dispersion of conductance and a large leakage current after repeated I-V measurements of 30-50 times, probably because of the granular structure of the deposited Al films. A chromium vertical array of two MIM junctions exhibited the linear I-V characteristics of a metal wire at room temperature just after fabrication. They exhibited the typical I-V characteristics of tunnel junctions after 300 degrees C annealing, probably because of the structural transition of chromium oxide films from the low-resistance CrO2 to the high-resistance Cr2O3.
引用
收藏
页码:1580 / 1583
页数:4
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