Deep submicron CMOS technology using top-edge round STI and dual gate oxide for low power 256 M-bit mobile DRAM

A new combination process, which consists of the pad oxide undercut to smoothen the active top-edge of the shallow trench isolation (STI) and the dual gate oxidation, was investigated for a 256 M-bit mobile dynamic random access memory (DRAM) with V-D 1.8 V. An I-DSAT of a thin oxide transistor (5.0 nm thickness) with a dual gate oxide (DGOX) increased by >12% compared to that with a single gate oxide (SGOX, 6.5 nm thickness). It was. also found that the boron doses of the thin oxide transistor with the DGOX increased by >30% and >45% for the n-channel metal oxide semiconductor field effect transistor (nMOSFET) and p-channel MOSFET (pMOSFET), respectively, in order to obtain the same threshold voltage (V-th) as that with the SGOX due to a decrease of oxide thickness and the segregation of boron into either the Si/SiO2 interface or the SiO2 layer for a longer gate oxidation time. The refresh characteristics of the 256 M-bit mobile, DRAM, fabricated with new combination process, were greatly improved compared to that with the SGOX transistors due to a decrease in the gate induced drain leakage current, an electrical stress release and the STI top-edge corner rounding in the cell array.