Optimum conditions of body effect factor and substrate bias in variable threshold voltage MOSFETs
被引:34
作者:
Koura, H
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机构:
Univ Tokyo, Inst Ind Sci, Minato Ku, Tokyo 1068558, JapanUniv Tokyo, Inst Ind Sci, Minato Ku, Tokyo 1068558, Japan
Koura, H
[1
]
论文数: 引用数:
h-index:
机构:
Takamiya, M
Hiramoto, T
论文数: 0引用数: 0
h-index: 0
机构:Univ Tokyo, Inst Ind Sci, Minato Ku, Tokyo 1068558, Japan
Hiramoto, T
机构:
[1] Univ Tokyo, Inst Ind Sci, Minato Ku, Tokyo 1068558, Japan
[2] Univ Tokyo, VLSI Design & Educ Ctr, Bunkyo Ku, Tokyo 1138656, Japan
来源:
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS
|
2000年
/
39卷
/
4B期
关键词:
body effect;
variable threshold voltage metal oxide semiconductor field effect transistor (VTMOS);
substrate bias;
low power;
active mode;
standby mode;
channel engineering;
D O I:
10.1143/JJAP.39.2312
中图分类号:
O59 [应用物理学];
学科分类号:
摘要:
The effects of body effect factor (gamma) and substrate bias (V-bs) in a variable threshold voltage metal oxide semiconductor field effect transistor (VTMOS) have been systematically examined by device simulation. The characteristics of a VTMOS are significantly affected by the value of gamma and the V-bs difference (Delta V-bs) between the active mode and the standby mode. Optimal gamma and Delta V-bs to Obtain higher on-current in the active mode and lower off-current in the standby mode are derived. When off-current in the active mode is limited, a larger Delta V-bs and smaller gamma are preferable to obtain a higher drive current. When gamma is fixed, \Delta V-bs\ should be as large as the breakdown and leakage current permits. When Delta V-bs is fixed for some reason, such as breakdown, the optimum gamma depends on the relationship between Delta V-bs and V-dd: gamma should be larger when a large \Delta V-bs\ can be applied, while it should be smaller when the \Delta V-bs\ is small. The scalability of VTMOS is also discussed and it is found that channel engineering is strongly required in a scaled VTMOS. These results will greatly help in designing ultra-low power VTMOS VLSIs, and the VTMOS could be expected to survive in the 50 nm generation depending on the scaling scenario and applications.