PREDICTION OF PRODUCT YIELD DISTRIBUTIONS FROM WAFER PARAMETRIC MEASUREMENTS OF CMOS CIRCUITS

A technique for predicting the yield distribution of CMOS circuits based on electrical parameter distributions is presented. This technique uses the mean and standard deviation of the measured threshold voltage and mobility of NMOS and PMOS transistors to project the yield of the circuit in a specified design window. The method of prediction is based on a probability model employing the bivariate normal distribution of the transistor parameters. The predicted yield is shown to be very sensitive to the design window specified by the circuit designer for proper functionality. The method thus provides a quantitative means of carrying out tradeoffs between design windows and final product yield.