OXIDATION-SHARPENED GATED FIELD EMITTER ARRAY PROCESS

被引：43

作者：

MCGRUER, NE

WARNER, K

SINGHAL, P

GU, JJ

CHUNG, C

机构：

[1] Department of Electrical and Computer Engineering, Northeastern University, Boston

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1991年 / 38卷 / 10期

关键词：

D O I：

10.1109/16.88531

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Structural and electrical characteristics of silicon field emitter arrays are reported. The process uses plasma etching and oxidation to form the field emission tips, and allows control of the aspect ratio of the devices. Processing limits and process latitude are discussed. We observe average currents of 0.3-mu-A/emitter in 1300-emitter arrays, and the emission is stable at 5 x 10(-8) torr. The arrays exhibit a soft failure behavior, where individual emission tips fail as the gate voltage is increased, but the array as a whole continues to operate.

引用

页码：2389 / 2391

页数：3

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