GATED PHOTOLUMINESCENCE METHOD FOR INTERFACE STATE DENSITY DETERMINATION

We have investigated the use of gated photoluminescence (PL) to estimate interface state density in III-V metal-insulator-semiconductor (MIS) structures. Low-temperature PL measurements have been recorded as a function of bias applied to the semi-transparent gate of a MIS diode. An analysis of these data resulted in surface state densities in the low 10(10)/cm2 eV range on sulfur passivated SiO2 coated InP. The present technique is more sensitive than the conventional 1 MHz capacitance-voltage (C-V) method, and less dependent on low leakage currents in the dielectric, when compared to the quasi-static C-V technique.