Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and +/-50 ps jitter

A fully integrated phase-locked loop (PLL) in a digital 0.5 um CMOS technology is described, The PLL has a locking range of 15 to 240 MHz, The static phase error is less than +/-100 ps with a peak-to-peak jitter of +/-50 ps at a 100 MHz output frequency, The PLL has a resistorless architecture achieved by the implementation of feedforward current injection into the current controlled oscillator.