Compatibility of NiSi in the self-aligned silicide process for deep submicrometer devices

The compatibility of NiSi in the self-aligned silicide (SALICIDE) process has been investigated for deep submicrometer device applications. In the SALICIDE process, the silicide formation should be laterally confined to the Si regions as source drain and gate regions of a metal-oxide semiconductor field effect transistor. It has been found that the NiSi produced by a one-step thermal annealing is confined laterally to the Si regions. The thin NiSi layer having a thickness of 26.7 nm has the sheet resistance of 6.2 Omega/square. The minimum value 6.2 Omega/square is achieved by the silicidation in the temperature range of 400-500 degrees C. A thickness dependence of electrical resistivity has been observed on NiSi layers thinner than 53.3 nm thick. The resistivity increases gradually with decreasing thickness. The NiSi layers thicker than 53.3 nm thick have a resistivity of 13.7 mu Omega cm comparable with that of bulk NiSi. No linewidth dependence of sheet resistance was observed. The 42.0 nm thick silicide on poly-Si having line widths from 0.2 to 16.0 mu m have a sheet resistance of 3.2 Omega/square. The thin silicides must be thermally stable through subsequent device processing. Silicide agglomeration has been observed after heat treatments of 600 degrees C. The silicide agglomeration results in an increase of the sheet resistance. However, the device processing after the formation of NiSi can be performed with temperatures lower than 600 degrees C. A few of the junctions silicided by using NiSi have a leakage current larger than that of the non-silicided junctions. This problem can be solved if a thermal annealing is done at 450 degrees C in H-2-N-2 before the Ni deposition. This result suggests that the annealing in H-2-N-2 acts effectively in order to prevent extra generation centers created in the depletion layer during the silicidation.