LATCHUP PATHS IN BIPOLAR INTEGRATED-CIRCUITS

被引：7

作者：

BAZE, MP

JOHNSTON, AH

机构：

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 1986年 / 33卷 / 06期

关键词：

D O I：

10.1109/TNS.1986.4334630

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：1499 / 1504

页数：6

共 10 条

[1]

[Anonymous], COMMUNICATION

[2]

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[3] AN SEM BASED SYSTEM FOR A COMPLETE CHARACTERIZATION OF LATCH-UP IN CMOS INTEGRATED-CIRCUITS [J].

CANALI, C ;

FANTINI, F ;

GIANNINI, M ;

SENIN, A ;

VANZI, M ;

ZANONI, E .

SCANNING, 1986, 8 (01) :20-33

[4] A SEM TECHNIQUE FOR EXPERIMENTALLY LOCATING LATCH-UP PATHS IN INTEGRATED-CIRCUITS [J].

DRESSENDORFER, PV ;

ARMENDARIZ, MG .

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1980, 27 (06) :1688-1693

[5]

ESTREICH DB, 1982, IEEE T COMP AIDED DE, V1

[6] LATCH-UP IN CMOS INTEGRATED-CIRCUITS [J].

GREGORY, BL ;

SHAFER, BD .

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1973, NS20 (06) :293-299

[7] EXPERIMENTAL METHODS FOR DETERMINING LATCHUP PATHS IN INTEGRATED-CIRCUITS [J].

JOHNSTON, AH ;

BAZE, MP .

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1985, 32 (06) :4260-4265

[8]

KANE PF, 1978, CHARACTERIZATION SOL, P114

[9] LATCH-UP CONTROL IN CMOS INTEGRATED-CIRCUITS [J].

OCHOA, A ;

DAWES, W ;

ESTREICH, D .

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1979, 26 (06) :5065-5068

[10]

SZE SM, 1983, VLSI TECHNOLOGY, P541

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