A 3-STEP METHOD FOR THE DE-EMBEDDING OF HIGH-FREQUENCY S-PARAMETER MEASUREMENTS

As the device size of the advanced bipolar transistors shrinks and the contact pad and interconnect linewidth is also scaled down, the series resistance and inductance of the interconnect cannot be neglected. We propose a general method of de-embedding for which typical parasitics associated with probe pads and interconnect-metal lines can be de-embedded from the measurement. This method includes the subtraction of the parasitic shunt y-parameters of the on-wafer open calibration pattern as well as the subtraction of the parasitic series z-parameters of the on-wafer open which are taken from measurements of the shorts and through. It is demonstrated that the calculated power loss for the pad and interconnect parasitics can be comparable to the power consumption of the advanced bipolar transistor at high frequencies (grater-than-or-equal-to 10 GHz). Therefore, a knowledge of the parasitic de-embedding circuit elements magnitude and type can aid the device engineer in the analysis of the error associated with de-embedding.