A 40 NM GATE LENGTH N-MOSFET

Forty nm gate length n-MOSFET's with ultrashallow source and drain junctions of around 10 nm are fabricated for the first time. In order to fabricate such small geometry MOSFET's, two special techniques have been adopted. One is a resist thinning technique using isotropic oxygen plasma ashing for the fabrication of 40 mn gate electrodes. The other is a solid phase diffusion technique from phosphorus doped silicated glass (PSG) for the fabrication of 10 mn source and drain junctions. The resulting 40 nm gate length n-MOSFET's operate quite normally at room temperature. Using these n-MOSFET's, we investigated short channel effects and current drivability in the 40 nn region at room temperature. We have also investigated hot-carrier related phenomena in the 40-nm region. Results indicate that the impact ionization rate increases slightly as the gate length is reduced to around 40 mn, and that both impact ionization rate and substrate current fall significantly as V-d falls below 1.5 V. This demonstrates that reliability as regards degradation due to hot carriers is not a serious problem even in the 40 mn region if Sh is less than or equal to 1.5 V.