RADIATION-HARDENED MICROELECTRONICS FOR SPACE APPLICATIONS

Radiation-hardened technology for space applications will be evaluated in light of its survivability in the total-dose, cosmic-ray, and solar flare environments normally encountered in space. Several examples of technology development programs will be summarized, including Sandia programs over the last two decades. Techniques for optimizing the radiation hardness of CMOS technologies for space will be discussed. For total-dose hardness, these techniques provide important information about the number of radiation-induced defects and their microscopic nature, and are used to identify manufacturing processes that play an important role in the fabrication of radiation-hardened integrated circuits (ICs). For example, the roles of high-temperature anneals, hydrogen and interfacial strain in the buildup of radiation-induced defects have received a great deal of attention, and many CMOS process flows have been designed to minimize hydrogen incorporation and reduce interfacial stress. Techniques for ensuring the tolerance of ICs to single-event phenomena (SEP) will be addressed, including the manufacture and control of high-resistivity polysilicon feedback resistors. Finally, some future trends in hardness assurance and testing that support more cost-effective qualification of ICs used in space will be covered. For total-dose, trends include wafer-level testing and X-ray irradiations; while for SEP, trends include Cf-252 and laser testing.